The present invention relates generally to a computer system and memory management, and more specifically, to a computer system that includes a processor with a cache for caching main memory that is managed by an enhanced memory management system.
Virtual machine (VM) concepts allow creating and running multiple operating environments on one physical server at the same time. Because each virtual environment requires its own operating system for running applications independently, a virtualization layer (hypervisor) provides a layer between the processing, storage and/or main memory, and networking hardware and the software that runs on it. This way, information technology cost may be lowered through increased efficiency and flexibility. Each virtual environment emulates a complete hardware system. However, virtual main memory areas need to be mapped to the real physical main memory of the underlying hardware system. Therefore, memory pages in the physical main memory may be shared between different processes, e.g., of different virtual machines or other processes. Memory pages in main memory which are currently not accessed are typically moved or pushed to disk and are not present in the physical main memory.
The underlying paging algorithm goal is therefore to move non-accessed pages to disk and to move required pages to the main memory. The basic problem may be described as efficiently identifying non-access pages to free up main memory. The underlying complexity exists due to shared memory pages and main memory. The same problem exists for a mapping of main memory pages to cache systems. There are currently some solutions for memory reference tracking available in order to make paging decisions.
U.S. Pat. No. 8,438,363 B1 describes a system, a method and a computer program product for virtualizing a processor including a virtualization system running on a computer system and controlling memory pages through hardware support for maintaining real paging structures.
U.S. Pat. No. 6,308,247 B1 discloses a page table entry management method and apparatus for providing a microkernel system with the ability to program a memory management unit on a PowerPC® family of processors. The PowerPC processors define a limited set of page table entries (PTEs) to maintain virtual to physical mappings. The page table entry management method and apparatus solve the problem of a limited number of PTEs by segment aliasing when two or more user processes share the segment of the memory.
However, almost all currently available architectures do not provide 2-way accurate reference information of the active page tracking. The available implementations provide fast memory access times, but slow checking/resetting of reference information. In the well-known Intel architecture, each page table entry has a reference bit embedded. In order to find the cumulative reference status of a page or all pages, table entries need to be found which requires quite some time. Pages of some dynamic shared library objects (DSOs), e.g., libc, are found in most all address spaces and thus, have many page table entries associated with them. Another architecture, the System Z® architecture uses a reference bit in a storage key, which is associated with each physical page frame. Special-purpose instructions are required; and quiesce operations need to automatically read/set the storage key, which in terms of performance can be relatively expensive, even after an optimization.
Hence, there is a need for better management of memory pages, particularly for identifying non-accessed pages to determine infrequent accessed pages as candidates for being moved from main memory to disk on a regular basis with low computing overhead.